1. Field of the Invention
The present invention relates to a data processing apparatus configured to detect the occurrence of an error during execution of data processing instructions. More particularly, the invention relates to a data processing apparatus having an error recovery unit configured to initiate re-execution of an instruction if an error is detected in association with the execution of that instruction.
2. Description of the Prior Art
It is known to provide a data processing apparatus with at least one error detection unit which is configured to take two samples of a given signal propagating in the data processing apparatus, the second sample being taken after a short delay period (but within the same clock cycle) with respect to the first sample, and to generate an error signal if the two samples differ. Such an error detection unit is for example of benefit in a data processing apparatus in which it may be attempted to operate at, or at least close to, its limits of reliable operation, for example in terms of clock speed, operating voltage, or even process reliability. An error signal generated by the error detection unit can indicate that the data processing apparatus has entered a regime in which the first sample of the signal has become unreliable (as determined with reference to the second sample), for example because a changing signal has been sampled slightly too early and therefore in a wrong state.
In a data processing apparatus which has an error detection unit it is further known to provide an error recovery unit which seeks to initiate an error recovery procedure which is carried out to seek to remedy adverse consequences resulting from that error. For example, in conjunction with an exception storage unit in the data processing apparatus, if the error detected is associated with a particular instruction, that instruction and any that follow it in the exception storage unit may be replayed in order to ensure that correct data processing operations in response to the data processing instructions are carried out.
The provision of an error detection unit enables the data processing apparatus to be operated in a regime where errors may occur, because a mechanism is provided for coping with such errors. Further, when the first and second samples of a signal taken by the error detection unit differ, it may be the case that the first sample was effectively taken too early, in particular before the error detection unit was stably configured to perform that first sampling. As a result some metastability of the error signal generated by the error detection unit can occur, the conventional solution to which is to provide stabilisation circuitry which re-samples the error signal a number of times (typically twice) in order that a reliable, stable error signal is produced.
Any circuitry in the data processing apparatus which is configured to respond to the error signal, for example error recovery circuitry, must therefore wait until the stabilisation circuitry has stabilised the error signal before it can be reliably acted upon. This delay (for example of two clock cycles) is a disadvantage when seeking to improve the operating speed of the data processing apparatus and accordingly it would be desirable to provide a data processing apparatus which could, at least in some instances, avoid such delays.